Typical IP deliverables

  • Hard Macro in Foundary [TSMC/UMC]  node [40nm/65nm] Process [GP/LP process] node
  • GDSII Layout database
  • LVS Net
    • Hard Macro in Foundary [TSMC] 65nm LP process node
    • GDSII Layout database
    • LVS Netlist (cdl) and LVS/DRC verification reports
    • LEF View with physical and pin information
    • Liberty (.lib) view
    • Verilog model
    • RTL files (encrypted)
    • Complete user manual with layout and  integration guidelines
    • Characterization report
    • Datasheet
    • Customer support
Advertisements
This entry was posted in Uncategorized. Bookmark the permalink.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s