Problem : How to optimize a design for low power
Power = CL * Vdd ^ 2 * f
CL: Load Capacitance ; Vdd : Supply Voltage; f: Operating frequency
Entire chip/circuit can be considered as a lumped capacitive load, which charges and discharges. Reducing this lumped capacitance value would reduce power. Optimize your design for number of flops, number of gates, states.
Vdd: Reducing the power supply by a factor of 2 reduces the power by a factor of 4. However power supply reduction comes with a price of making the design slower. Consider reducing supply voltage on non-critical paths.
F: Reducing the number of computations and there by reducing the frequency at which the flops/capacitance switch reduces the power