Monthly Archives: February 2012

useful links

1.Async FIFO design Technique Async Pointers : Simulation and Synthesis Techniques for Asynchronous FIFO Design Sync Pointers : Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons 2. CDC design and Verification : http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf 3. Sync and Async Resets … Continue reading

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8b10b encoding

http://www.latticesemi.com/lit/docs/refdesigns/rd1012.pdf  

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Typical IP deliverables

Hard Macro in Foundary [TSMC/UMC]  node [40nm/65nm] Process [GP/LP process] node GDSII Layout database LVS Net Hard Macro in Foundary [TSMC] 65nm LP process node GDSII Layout database LVS Netlist (cdl) and LVS/DRC verification reports LEF View with physical and … Continue reading

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USB2.0 Vs USB3.0

High speed data is clocked at 480.00Mb/s with a data signalling tolerance of ± 500ppm. Full speed data is clocked at 12.000Mb/s with a data signalling tolerance of ±0.25% or 2,500ppm. Low speed data is clocked at 1.50Mb/s with a … Continue reading

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LTSSM operation

Detect.idle -> Detect.Active -> Polling.Active – > Polling.Configuration  -> Configuration – > Lane.num -> Lane.Width -> Config.complete -> L0 -> L1 -> L3 – L0        

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Signal Integrity issues

http://www.allaboutcircuits.com/vol_2/chpt_14/6.html

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What’s metastability?

When a flop’s setup and hold time are not met, a flop enters into a metastable state. Data is captured at a time when it’s neither a zero nor a one and struggles its way inside the cross coupled inverter … Continue reading

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